Circuit board and manufacturing method thereof
US9591753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Oct 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/072
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.