Identifying stale entries in address translation cache
US9594680B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.