Memory device and systems and methods for selecting memory cells in the memory device
US9595335B2 · kind B2 · utility
0Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.