Floating gate separation in NAND flash memory

US9595444B2 · kind B2 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventors

• Toshiya Yokota · Yokkaichi, JP
• Atsushi Shimoda · Hiratsuka, JP
• Takuya Sakurai · Yokohama, JP

Key dates

• Filing date: May 14, 2015
• Grant date: Mar 14, 2017
• Expiry date: May 14, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/01

Abstract

A method of forming a NAND flash memory includes anisotropically etching trenches of a gate stack down to an intermediate level in a floating gate polysilicon layer, leaving remaining portions of the floating gate polysilicon over the gate dielectric layer. Subsequently, forming a protective layer along exposed sides of the trenches. Then, electrically separating individual floating gates by a selective process that is directed to the remaining portions of the floating gate polysilicon layer exposed by trenches.