Patent · US Active

Chip package method and package assembly

US9595453B2 · kind B2 · utility

1Cited by

2References

10Claims

0Family size

Assignee

Silergy Semiconductor Technology (Hangzhou) Ltd. · CN

Inventors

Xiaochun Tan · Bellevue, US
Jiaming Ye · Hangzhou City, CN

Key dates

Filing date	Jun 10, 2016
Grant date	Mar 14, 2017
Priority date	—
Expiry date	Jun 10, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/00014
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a chip package method and a package assembly. A metal plate is micro-etched to form trenches having a predetermined depth. A metallic conductor is formed as a leadframe by filling the trenches with a material having relatively small adhesion with the metal plate. In such manner, the metal plate can be peeled off from a package body after the chip is electrically coupled to the metallic conductor and encapsulated by a molding process. A bottom of the metallic conductor is exposed from the package body. A chip package is thus completed. It simplifies a manufacture process for forming a chip package, reduces manufacture cost, and increases reliability of the chip package.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.