Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
US9595530B1 · kind B1 · utility
184Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 7, 2016 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.