Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof
US9599672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Mar 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.