Aligning FIFO pointers in a data communications lane of a serial link
US9600232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2013 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.