Matrix multiplication operations using pair-wise load and splat operations
US9600281B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2010 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Oct 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A pair-wise load and splat operation is performed to load a pair of scalar values of a second vector operand and replicate the pair of scalar values within a second target vector register. An operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product is accumulated with other partial products and a resulting accumulated partial product is stored. This operation may be repeated for a second pair of scalar values of the second vector operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.