Method and apparatus for debugging HDL design code and test program code
US9600398B2 · kind B2 · utility
0Cited by
3References
14Claims
0Family size
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Key dates
| Filing date | Oct 29, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Oct 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values generated by executing the test program code and the design code during a previously executed simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.