Secure virtual access for real-time embedded devices
US9600412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2011 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The secure space may be used to protect data of the privileged clients from being accessed by the non-privileged clients. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space. The page may correspond to a particular one of the clients that won the arbitration. The page may translate into the secure space if the particular client is one of the privileged clients. The page may also translate outside the secure space if the particular client is one of the non-privileged clients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.