Apparatus and method for implementing a multi-level memory hierarchy

US9600416B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Raj K. Ramanujan · Federal Way, US
• Rajat Agarwal · Portland, US
• Kai Cheng · Portland, US
• Taarinya Polepeddi · London, GB
• Camille C. Raad · Folsom, US
• David J. Zimmerman · Cameron Park, US
• Muthukumar P. Swaminathan · Folsom, US
• Dimitrios Ziakas · Hillsboro, US
• Mohan J. Kumar · Beaverton, US
• Bassam N. Coury · Portland, US
• Glenn J. Hinton · Portland, US

Key dates

• Filing date: Sep 30, 2011
• Grant date: Mar 21, 2017
• Expiry date: Dec 24, 2031

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”