Block-level code coverage in simulation of circuit designs
US9600613B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Sep 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be executed for different sets of values of the set of configuration parameters. The circuit design is simulated for a first set of values for the configuration parameters. The simulation is performed using a model that omits code blocks that describe sets of operations that will not be executed. The determined expressions are evaluated to determine whether or not each identified code block was realized in the simulation model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.