Low voltage difference operated EEPROM and operating method thereof
US9601202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.