Three-dimensional semiconductor devices and fabricating methods thereof
US9601204B2 · kind B2 · utility
4Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Oct 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.