Semiconductor memory device
US9601211B1 · kind B1 · utility
4Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Apr 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include a memory cell array, two or more global word lines, and two or more path circuits. The two or more global word lines may be coupled to word lines in parallel. At least one of the two or more path circuits may be coupled between portions of each word line portions of each word line. Each path circuit may couple one of the global word lines to one of the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.