Semiconductor device including redundancy cell array
US9601216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.