Semiconductor manufacturing for forming bond pads and seal rings
US9601354B2 · kind B2 · utility
2Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jul 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.