Nonvolatile semiconductor memory device and method of manufacturing the same
US9601370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Mar 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.