Integrated high-K/metal gate in CMOS process flow
US9601388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jan 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.