Vertical field effect transistors having epitaxial fin channel with spacers below gate structure
US9601491B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.