Tie-off circuit with output node isolation for protection from electrostatic discharge (ESD) damage
US9601921B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | May 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to electrostatic discharge (ESD) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (FETs), a first internal node, a second internal node, a first output node and a second output node. A node isolation circuit is connected to the first output node and the second output node of the tie-off circuit. The node isolation circuit includes a first FET with a third output node and a second FET with a fourth output node. The third output node and the fourth output node are electrically isolated from the first internal node and the second internal node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.