Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor
US9606797B2 · kind B2 · utility
11Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.