Tracing data from an asynchronous interface
US9606891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Jun 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.