Method and apparatus for calculating delay timing values for an integrated circuit design
US9607117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2013 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Jan 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.