Memory device and electronic apparatus including the same
US9607667B1 · kind B1 · utility
10Cited by
0References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 25, 2016 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Feb 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.