Hardware command training for memory using write leveling mechanism
US9607714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.