Patent · US Active

Silicon via with amorphous silicon layer and fabrication method thereof

US9607895B2 · kind B2 · utility

0Cited by

4References

19Claims

0Family size

Assignee

Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

Zuopeng He · Shanghai, CN
Hongbo Zhao · Nanjing, CN

Key dates

Filing date	May 27, 2015
Grant date	Mar 28, 2017
Priority date	—
Expiry date	May 27, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and forming a deep hole in the substrate from the upper surface. The method also includes forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers. Further, the method includes forming a barrier layer having a preferred orientation along the (111) crystal face on the barrier layer. Further, the method also includes forming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the through hole.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.