Pin grid interposer
US9607937B2 · kind B2 · utility
0Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2011 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Mar 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.