Patent · US Active

Method of wafer-scale integration of semiconductor devices and semiconductor device

US9608035B2 · kind B2 · utility

0Cited by

2References

5Claims

0Family size

Assignee

AMS AG · AT

Inventors

Cathal Cassidy · Okinawa, JP
Joerg Siegert · Graz, AT
Franz Schrank · Graz, AT

Key dates

Filing date	Apr 5, 2013
Grant date	Mar 28, 2017
Priority date	—
Expiry date	Apr 5, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/37001
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.