Method and structure to reduce parasitic capacitance in raised source/drain silicon-on-insulator devices

US9608080B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• STMicroelectronics (Crolles 2) SAS · FR

Inventors

• Ahmet S. Ozcan · Pleasantville, US
• Emmanuel Petitprez · Grenoble, FR

Key dates

• Filing date: Mar 5, 2015
• Grant date: Mar 28, 2017
• Expiry date: Mar 19, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.