Ahmet S. Ozcan
88Patents
6h-index
76Co-inventors
71Inventor score
Filing activity: Jun 10, 2008 → Sep 21, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8603881B1 | Raised trench metal semiconductor alloy formation | Electricity | 10 | Active |
| US8598006B2 | Strain preserving ion implantation methods | Electricity | 9 | Active |
| US8278200B2 | Metal-semiconductor intermixed regions | Electricity | 8 | Active |
| US8614107B2 | Liner-free tungsten contact | Electricity | 8 | Active |
| US8030154B1 | Method for forming a protection layer over metal semiconductor contact and structure formed thereon | Electricity | 7 | Active |
| US8349716B2 | Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device | Electricity | 7 | Active |
| US7759208B1 | Low temperature ion implantation for improved silicide contacts | Electricity | 6 | Active |
| US9379012B2 | Oxide mediated epitaxial nickel disilicide alloy contact formation | Electricity | 6 | Active |
| US8614106B2 | Liner-free tungsten contact | Electricity | 5 | Active |
| US8796099B2 | Inducing channel strain via encapsulated silicide formation | Electricity | 5 | Active |
| US10269714B2 | Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements | Electricity | 4 | Active |
| US7993987B1 | Surface cleaning using sacrificial getter layer | Electricity | 4 | Active |
| US9093425B1 | Self-aligned liner formed on metal semiconductor alloy contacts | Electricity | 3 | Active |
| US8927422B2 | Raised silicide contact | Electricity | 3 | Active |
| US10546941B2 | Forming thermally stable salicide for salicide first contacts | Electricity | 3 | Active |
| US9236345B2 | Oxide mediated epitaxial nickel disilicide alloy contact formation | Electricity | 3 | Active |
| US10685888B2 | Low resistance source-drain contacts using high temperature silicides | Electricity | 2 | Active |
| US11101219B2 | Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements | Electricity | 2 | Active |
| US8021971B2 | Structure and method to form a thermally stable silicide in narrow dimension gate stacks | Electricity | 2 | Active |
| US9882005B2 | Fully depleted silicon-on-insulator device formation | Electricity | 2 | Active |
| US10985105B2 | Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements | Electricity | 2 | Active |
| US9786547B2 | Channel silicon germanium formation method | Electricity | 2 | Active |
| US8829645B2 | Structure and method to form e-fuse with enhanced current crowding | Electricity | 1 | Active |
| US10943988B2 | Thermally stable salicide formation for salicide first contacts | Electricity | 1 | Active |
| US8456011B2 | Method to control metal semiconductor micro-structure | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.