Phase-locked loop having sub-sampling phase detector

US9608644B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Mayank Raj · San Jose, US
• Parag Upadhyaya · Los Gatos, US
• Adebabay M. Bekele · San Jose, US

Key dates

• Filing date: Jun 3, 2016
• Grant date: Mar 28, 2017
• Expiry date: Jun 3, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/0895
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control voltage, a sub-sampling phase detector configured to receive a reference clock and the output clock, and a phase frequency detector configured to receive the reference clock and a feedback clock. The PLL circuit includes a charge pump configured to generate a charge pump current, a multiplexer circuit configured to select either output of the sub-sampling phase detector or output of the phase frequency detector to control the charge pump, and a lock detector configured to receive the reference clock, the feedback clock, and the output of the phase frequency detector to control the multiplexer. The PLL circuit includes a loop filter configured to filter the charge pump current and generate the oscillator control voltage, and a frequency divider configured to generate the reference clock from the output clock.