Testing memory devices with parallel processing operations
US9612272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Feb 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.