Solid state drive controller
US9612775B1 · kind B1 · utility
2Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jan 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.