Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems
US9612929B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2016 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jan 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.