Patent · US Active

Providing autonomous self-testing of a processor

US9612930B2 · kind B2 · utility

5Cited by

3References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Vedvyas Shanbhogue · Austin, US
Eric Rasmussen · Boynton Beach, US
Deep Buch · Folsom, US
Gordon McFadden · Hillsboro, US
Kameswar Subramaniam · Austin, US
Amy L. Santoni · Scottsdale, US
Willard M. Wiseman · Tigard, US
Bret L. Toll · Hillsboro, US

Key dates

Filing date	Jun 12, 2015
Grant date	Apr 4, 2017
Priority date	—
Expiry date	Aug 18, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1433
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.