Page cache device and method for efficient mapping
US9612975B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the inventive concept can include a multi-stage mapping technique for a page cache controller. For example, a gigantic virtual page address space can be mapped to a physical page address efficiently, both in terms of time and space. An internal mapping module can implement a mapping technique for kernel virtual page address caching. In some embodiments, the mapping module can include integrated balanced skip lists and page tables for mapping sparsely populated kernel virtual page address space or spaces to physical block (i.e., page) address space or spaces. The mapping module can automatically and dynamically convert one or more sections from a skip list to a page table, or from a page table to a skip list. Thus, the kernel page cache can be extended to have larger secondary memory using volatile or non-volatile page cache storage media.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.