Dynamically reconfigurable analog routing circuits and methods for system on a chip
US9612987B2 · kind B2 · utility
3Cited by
83References
19Claims
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Key dates
| Filing date | May 7, 2010 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jun 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.