Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit
US9613175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.