Buffer chain management for alleviating routing congestion
US9613176B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jun 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.