Patent · US Active

Method for hiding texture latency and managing registers on a processor

US9613389B2 · kind B2 · utility

1Cited by

3References

3Claims

0Family size

Assignee

SHENZHEN ZHONGWEIDIAN TECHNOLOGY LIMITED · CN

Inventors

Simon Moy · Mountain View, US
Shihao Wang · Tangxia, CN
Zhengqian Qiu · Tangxia, CN

Key dates

Filing date	Dec 14, 2011
Grant date	Apr 4, 2017
Priority date	—
Expiry date	Dec 14, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with the same length, binding the register sets to chipsets of the processor at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a Program Counter (PC) value in the case of return; and returning texture detail and allowing the shader thread to restart running.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.