Methods for setting a resistance of programmable resistance memory cells and devices including the same
US9613693B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Oct 29, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Oct 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method can include applying a first electric field to a plurality of memory elements that are programmable between at least two different resistance states; verifying whether the memory elements have a resistance outside of a first limit; for memory elements that are not outside of the first limit, applying a second electric field of a same direction as the first electric field, and not applying the second electric field to those memory elements that are outside the first limit; and verifying whether the memory elements receiving the second electric field have a resistance outside of a second limit; wherein the second limit is between the first limit and a read limit, where a memory element having a resistance below the read limit is determined to store one data value, and a memory element having a resistance above the read limit is determined to store another data value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.