Detection system for detecting fail block using logic block address and data buffer address in a storage tester
US9613718B2 · kind B2 · utility
0Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing data read from SSD test without expected data buffer. The system comprises a device driver for controlling HBA; a request processor for reading the request to Root Complex and transmitting the result to a data engine; and the data engine for generating data to be transmitted to SSD and comparing the read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.