Method and apparatus for reverse memory sparing
US9613722B2 · kind B2 · utility
2Cited by
1References
24Claims
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Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.