Patent · US Active

Bridge line structure for bit line connection in a three-dimensional semiconductor device

US9613975B2 · kind B2 · utility

15Cited by
1References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 31, 2015
Grant dateApr 4, 2017
Priority date
Expiry dateMar 31, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D89/10

Abstract

A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.