Semiconductor memory device and method of manufacturing the same
US9613979B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Manufactured in a method of manufacturing according to an embodiment is a semiconductor memory device including: control gate electrodes; a semiconductor layer; and a charge accumulation layer. In this method of manufacturing, inter-layer insulating layers and sacrifice layers are stacked alternately, an opening that penetrates the inter-layer insulating layers and sacrifice layers is formed, a first insulating layer, the charge accumulation layer, and the semiconductor layer are formed in the opening, the sacrifice layer and part of the first insulating layer are removed, and the control gate electrodes are formed. An internal diameter of the opening is smaller the more downwardly a portion of the opening is positioned. A film thickness of the first insulating layer is smaller the more downwardly a portion of the first insulating layer is positioned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.