OTP MRAM
US9614144B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Dec 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
Techniques for forming OTP memory elements with reduced breakdown voltage are provided. In one aspect, a method of forming an OTP MRAM element includes the steps of: creating a substrate having surface topology; and forming the OTP MRAM element on the substrate over the surface topology, wherein the OTP MRAM element comprises a first magnetic metal layer and a second metal magnetic layer separated by a tunnel barrier, and wherein by forming the OTP MRAM element over the surface topology the tunnel barrier has both a first thickness T1 and second thickness T2, wherein T1 is greater than T2. A method of forming a device having both MTP MRAM and OTP MRAM elements is provided, as is an MRAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.