Accurate sample latch offset compensation scheme
US9614502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Aug 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7203
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.