Programmable CPU register hardware context swap mechanism
US9619231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.